用VHDL设计的任意频率分频器

Sometimes I need to generate a clock at a lower frequency than the main clock driving the FPGA. If the ratio of the frequencies is a power of 2, the logic is easy. If the ratio is an integer N, then a divide-by-N counter is only a little harder. But if the ratio isn"t an integer, a little (and I mean a little) math is required. Note that the new clock will have lots of jitter: there"s no escaping that. But it will have no drift, and for some applications that"s what counts. If you have a clock A at frequency a, and want to make a clock B at some lower frequency b (that is, b a), then something like: d = 0; forever { Wait for clock A. if (d 1) { d += (b/a); } else { d += (b/a) - 1; /* getting here means tick for clock B */ } } but comparison against zero is easier, so subtract 1 from d: d = 0; forever { Wait for clock A. if (d 0) { d += (b/a); } else { d += (b/a) - 1; /* getting here means tick for clock B */ } } want an integer representation, so multiply everything by a: d = 0; forever { Wait for clock A. if (d 0) { d += b; } else { d += b - a; /* getting here means tick for clock B */ } } For example. I just bought a bargain batch of 14.1523MHz oscillators from BG but I need to generate a 24Hz clock. So a=14152300 and b=24: d = 0; forever { Wait for clock A. if (d 0) { d += 24; } else { d += 24 - 14152300; /* getting here means tick for clock B */ } } For a hardware implementation I need to know how many bits are needed for d: here it"s 24 bits to hold the largest value (-14152300) plus one more bit for the sign. In VHDL this looks like: signal d, dInc, dN : std_logic_vector(24 downto 0); process (d) begin if (d(24) = "1") then dInc = 0000000000000000000011000; -- (24) else dInc = 1001010000000110110101100; -- (24 - 14152300) end if; end process; dN = d + dInc; process begin wait until A"event and A = "1"; d = dN; -- clock B tick whenever d(24) is zero end process;

关键词： VHDL任意频率分频器